ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
0: Input
0
1: Output
P2DIR.3
Direction Control
1
From Module
Pad Logic
P2.3/CA0/TA1
0
P2OUT.3
Module X OUT
1
P2IN.3
EN
Bus Keeper
Module X IN
P2IRQ.3
D
P2IE.3
Interrupt
Edge
Select
EN
Set
CAPD.3
Q
P2IFG.3
Comparator_A
CAF
CAEX
P2CA
Interrupt
Flag
P2IES.3
P2SEL.3
CAREF
+
CCI1B
To Timer_A3
−
P2SEL.4
Reference Block
P2IES.4
CAREF
Interrupt
Flag
Edge
Select
Interrupt
P2IFG.4
Set
Q
EN
CAPD.4
P2IRQ.4
Module X IN
P2IE.4
D
Bus Keeper
EN
P2IN.4
1
Module X OUT
P2OUT.4
0
1
P2.4/CA1/TA2
Pad Logic
From Module
Direction Control
P2DIR.4
1: Output
0: Input
0
P2SEL.4
DIRECTION
CONTROL
PnSel.x
PnDIR.x
PnOUT.x MODULE X OUT PnIN.x
MODULE X IN
PnIE.x PnIFG.x PnIES.x
FROM MODULE
†
†
P2Sel.3
P2Sel.4
P2DIR.3
P2DIR.4
P2DIR.3
P2DIR.4
P2OUT.3
P2OUT.4
Out1 signal
P2IN.3
P2IN.4
unused
unused
P2IE.3 P2IFG.3 P2IES.3
P2IE.4 P2IFG.4 P2IES.4
Out2 signal
†
Signal from Timer_A
42
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