ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
Timer_B interrupt vector
Timer_B control
WDTCTL
TBIV
0120h
011Eh
0180h
0182h
0184h
0186h
0188h
018Ah
018Ch
018Eh
0190h
0192h
0194h
0196h
0198h
019Ah
019Ch
019Eh
012Eh
0160h
0162h
0164h
0166h
0168h
016Ah
016Ch
016Eh
0170h
0172h
0174h
0176h
0178h
017Ah
017Ch
017Eh
013Eh
013Ch
013Ah
0138h
0136h
0134h
0132h
0130h
Timer_B7/
Timer_B3
(see Note 1)
TBCTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
Timer_B register
TBCCTL0
TBCCTL1
TBCCTL2
TBCCTL3
TBCCTL4
TBCCTL5
TBCCTL6
TBR
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Capture/compare register 3
Capture/compare register 4
Capture/compare register 5
Capture/compare register 6
Timer_A interrupt vector
Timer_A control
TBCCR0
TBCCR1
TBCCR2
TBCCR3
TBCCR4
TBCCR5
TBCCR6
TAIV
Timer_A3
TACTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Reserved
TACCTL0
TACCTL1
TACCTL2
Reserved
Reserved
Reserved
Timer_A register
TAR
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Reserved
TACCR0
TACCR1
TACCR2
Reserved
Reserved
Reserved
Hardware
Multiplier
(MSP430x14x and
MSP430x14x1
only)
Sum extend
SUMEXT
RESHI
RESLO
OP2
Result high word
Result low word
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
MACS
MAC
MPYS
MPY
NOTE 1: Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.
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