ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢄ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢃ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢃ ꢆꢇ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
timer_B7 (MSP430x14x and MSP430x14x1 Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
†
Timer_B3/B7 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
43 - P4.7
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
43 - P4.7
36 - P4.0
36 - P4.0
36 - P4.0
TB0
ADC12 (internal)
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
DV
DV
SS
V
CC
CC
37 - P4.1
37 - P4.1
TB1
TB1
CCI1A
CCI1B
GND
37 - P4.1
ADC12 (internal)
DV
SS
DV
V
CC
CC
38 - P4.2
38 - P4.2
TB2
TB2
CCI2A
CCI2B
GND
38 - P4.2
39 - P4.3
40 - P4.4
41 - P4.5
42 - P4.6
DV
SS
DV
V
CC
CC
39 - P4.3
39 - P4.3
TB3
TB3
CCI3A
CCI3B
GND
DV
SS
DV
V
CC
CC
40 - P4.4
40 - P4.4
TB4
TB4
CCI4A
CCI4B
GND
DV
SS
DV
V
CC
CC
41 - P4.5
41 - P4.5
TB5
TB5
CCI5A
CCI5B
GND
DV
SS
DV
V
CC
CC
42 - P4.6
TB6
ACLK (internal)
CCI6A
CCI6B
GND
DV
SS
CC
DV
V
CC
†
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
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