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MSP430F149IPMR 参数 Datasheet PDF下载

MSP430F149IPMR图片预览
型号: MSP430F149IPMR
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器和处理器外围集成电路装置PC时钟
文件页数/大小: 65 页 / 1221 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃ ꢆꢈ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢆ ꢇ  
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ  
SLAS272F − JULY 2000 − REVISED JUNE 2004  
comparator_A  
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,  
battery−voltage supervision, and monitoring of external analog signals.  
ADC12 (Not implemented in the MSP430x14x1)  
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR  
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The  
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without  
any CPU intervention.  
timer_A3  
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple  
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.  
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare  
registers.  
Timer_A3 Signal Connections  
Input Pin Number Device Input Signal Module Input Name  
Module Block  
Module Output Signal  
Output Pin Number  
12 - P1.0  
TACLK  
ACLK  
TACLK  
ACLK  
Timer  
NA  
SMCLK  
TAINCLK  
TA0  
SMCLK  
INCLK  
CCI0A  
CCI0B  
GND  
21 - P2.1  
13 - P1.1  
22 - P2.2  
13 - P1.1  
17 - P1.5  
27 - P2.7  
TA0  
CCR0  
CCR1  
CCR2  
TA0  
TA1  
TA2  
DV  
DV  
SS  
V
CC  
CC  
14 - P1.2  
15 - P1.3  
TA1  
CAOUT (internal)  
CCI1A  
CCI1B  
GND  
14 - P1.2  
18 - P1.6  
DV  
23 - P2.3  
SS  
CC  
DV  
V
CC  
ADC12 (internal)  
15 - P1.3  
TA2  
ACLK (internal)  
CCI2A  
CCI2B  
GND  
19 - P1.7  
DV  
24 - P2.4  
SS  
CC  
DV  
V
CC  
timer_B3 (MSP430x13x Only)  
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple  
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.  
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare  
registers.  
18  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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