MSP430F530x, MSP430F5310
SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
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Pad Logic
to XT1
P5REN.5
DVSS
DVCC
0
1
1
P5DIR.5
0
1
P5OUT.5
0
1
Module X OUT
P5.5/XOUT
P5DS.5
0: Low drive
1: High drive
P5SEL.5
XT1BYPASS
P5IN.5
Bus
Keeper
EN
D
Module X IN
Table 52. Port P5 (P5.4 and P5.5) Pin Functions
CONTROL BITS/SIGNALS(1)
PIN NAME (P7.x)
P5.4/XIN
x
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
4
P5.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
X
X
X
X
0
1
X
0
1
XIN crystal mode(2)
XIN bypass mode(2)
P5.5 (I/O)
XOUT crystal mode(3)
P5.5 (I/O)(3)
X
X
P5.5/XOUT
5
I: 0; O: 1
X
X
(1) X = Don't care
(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
78
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