MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 –MARCH 2013
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Timer_A3 (TA0, TA1)
Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
DA38
RHA40
DA38
RHA40
P1.0 - 31
P1.0-29
TACLK
ACLK
SMCLK
TACLK
TA0.0
ACLK
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
P2.1 - 9
P1.1 - 32
P2.2 - 10
P2.1 - 7
P1.1 - 30
P2.2 - 8
P1.1- 32
P2.2 - 10
P1.5 - 36
P1.1 - 30
P2.2 - 8
TA0
TA1
TA2
P1.5 - 34
VCC
VCC
P1.2 - 33
P2.3 - 29
P1.2 - 31
P2.3 - 27
TA0.1
TA0.1
VSS
CCI1A
CCI1B
GND
P1.2 - 33
P2.3 - 29
P1.6 - 37
P1.2 - 31
P2.3 - 27
P1.6 - 35
VCC
VCC
P1.3 - 34
P1.3 - 32
TA0.2
ACLK (internal)
VSS
CCI2A
CCI2B
GND
P1.3 - 34
P2.4 - 30
P1.7 - 38
P1.3 - 32
P2.4 - 28
P1.7 - 36
VCC
VCC
Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
MODULE
BLOCK
DA38
RHA40
DA38
RHA40
P2.0 - 8
P2.0 - 6
TACLK
ACLK
SMCLK
TACLK
TA1.0
TA1.0
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
PinOsc
PinOsc
P2.5 - 3
P2.5 - 40
P2.5 - 3
P3.6 - 27
P3.7 - 28
P2.5 - 40
P3.6 - 25
P3.7 - 26
TA0
TA1
TA2
VCC
VCC
P3.6 - 27
P3.6 - 25
TA1.1
CAOUT
VSS
CCI1A
CCI1B
GND
VCC
VCC
P3.7 - 28
PinOsc
P3.7 - 26
PinOsc
TA1.2
TA1.2
VSS
CCI2A
CCI2B
GND
VCC
VCC
14
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