MSP430G2955
MSP430G2855
MSP430G2755
www.ti.com
SLAS800 –MARCH 2013
Table 16. Peripherals With Byte Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
USCI_B0
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
011Ah
0118h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
04Ah
04Bh
049h
048h
05Bh
05Ah
059h
053h
058h
057h
056h
044h
011h
01Fh
01Eh
01Dh
01Ch
043h
010h
01Bh
01Ah
019h
018h
USCI B0 I2C Interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
CAPD
USCI_A0
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P4 selection 2
ADC10
Comparator_A+
CACTL2
CACTL1
Basic Clock System+
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P4SEL2
Port P4
Port P4 resistor enable
Port P4 selection
P4REN
P4SEL
Port P4 direction
P4DIR
Port P4 output
P4OUT
Port P4 input
P4IN
Port P3
Port P3 selection 2
P3SEL2
Port P3 resistor enable
Port P3 selection
P3REN
P3SEL
Port P3 direction
P3DIR
Port P3 output
P3OUT
Port P3 input
P3IN
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: MSP430G2955 MSP430G2855 MSP430G2755
TI [ TEXAS INSTRUMENTS ]
