MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 –MARCH 2013
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw-0
NMIIE
rw-0
OFIE
rw-0
WDTIE
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
NMIIE
ACCVIE
Address
7
6
5
4
3
2
1
0
01h
UCB0TXIE
rw-0
UCB0RXIE
rw-0
UCA0TXIE
rw-0
UCA0RXIE
rw-0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive interrupt enable
USCI_A0 transmit interrupt enable
USCI_B0 receive interrupt enable
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw-0
RSTIFG
rw-(0)
PORIFG
rw-(1)
OFIFG
rw-1
WDTIFG
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
RSTIFG
NMIIFG
Power-on reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
Address
03h
7
6
5
4
3
2
1
0
UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
10
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