MSP430G2x53
MSP430G2x13
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SLAS735A –APRIL 2011–REVISED MAY 2011
Timer_A3 (TA0, TA1)
Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PW20, N20
PW28
RHB32
PW20, N20
PW28
RHB32
P1.0-2
P1.0-2
P1.0-31
TACLK
ACLK
SMCLK
TACLK
TA0.0
ACLK
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
PinOsc
P1.1-3
PinOsc
P1.1-3
PinOsc
P1.1-1
P1.1-3
P1.5-7
P1.1-3
P1.5-7
P3.4-15
P1.1-1
P1.5-5
P3.4-14
TA0
TA1
TA2
VCC
VCC
P1.2-4
PinOsc
P1.2-4
P1.2-2
TA0.1
CAOUT
VSS
CCI1A
CCI1B
GND
P1.2-4
P1.6-14
P2.6-19
P1.2-4
P1.6-22
P2.6-27
P3.5-19
P3.0-9
P1.2-2
P1.6-21
P2.6-26
P3.5-18
P3.0-7
VCC
VCC
P3.0-9
PinOsc
P3.0-7
PinOsc
TA0.2
TA0.2
VSS
CCI2A
CCI2B
GND
P3.6-20
P3.6-19
VCC
VCC
Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PW20, N20
PW28
RHB32
PW20, N20
PW28
RHB32
-
P3.7-21
P3.7-20
TACLK
ACLK
SMCLK
TACLK
TA1.0
TA1.0
VSS
TACLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
NA
-
P3.7-21
P2.0-10
P2.3-16
P3.7-20
P2.0-9
P2.0-8
P2.3-11
P2.0-8
P2.0-10
P2.3-16
P3.1-8
P2.0-9
P2.3-15
P3.1-6
P2.3-12
P2.3-11
TA0
TA1
TA2
VCC
VCC
P2.1-9
P1.7-23
P2.2-12
P2.1-10
P2.2-11
TA1.1
TA1.1
VSS
CCI1A
CCI1B
GND
P2.1-9
P1.7-23
P2.2-12
P3.2-13
P2.1-10
P2.2-11
P3.2-12
P2.2-10
P2.2-10
VCC
VCC
P2.4-12
P2.5-13
P2.4-17
P2.5-18
P2.4-16
P2.5-17
TA1.2
TA1.2
VSS
CCI2A
CCI2B
GND
P2.4-12
P2.5-13
P2.4-17
P2.5-18
P3.3-14
P2.4-16
P2.5-17
P3.3-13
VCC
VCC
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