MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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Table 15. Peripherals With Byte Access
REGISTER
NAME
MODULE
REGISTER DESCRIPTION
OFFSET
USCI_B0
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
CAPD
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
011Ah
0118h
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
04Ah
04Bh
049h
048h
05Bh
05Ah
059h
053h
058h
057h
056h
043h
010h
01Bh
01Ah
019h
018h
042h
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
USCI B0 I2C Interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
Port P3 selection 2. pin
Port P3 resistor enable
Port P3 selection
ADC10
(MSP430G2x53 devices only)
Comparator_A+
CACTL2
CACTL1
Basic Clock System+
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
P3SEL2
Port P3
(28-pin PW and 32-pin RHB only)
P3REN
P3SEL
Port P3 direction
P3DIR
Port P3 output
P3OUT
Port P3 input
P3IN
Port P2
Port P2 selection 2
P2SEL2
Port P2 resistor enable
Port P2 selection
P2REN
P2SEL
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
P2IE
P2IES
P2IFG
Port P2 direction
P2DIR
Port P2 output
P2OUT
Port P2 input
P2IN
18
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