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MSP430FR5732IRGER 参数 Datasheet PDF下载

MSP430FR5732IRGER图片预览
型号: MSP430FR5732IRGER
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 109 页 / 1238 K
品牌: TI [ TEXAS INSTRUMENTS ]
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MSP430FR573x  
MSP430FR572x  
www.ti.com  
SLAS639D JULY 2011REVISED AUGUST 2012  
Schmitt-Trigger Inputs – General Purpose I/O  
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
2 V  
3 V  
2 V  
3 V  
2 V  
3 V  
MIN  
0.80  
1.50  
0.45  
0.75  
0.25  
0.30  
TYP  
MAX UNIT  
1.40  
V
VIT+  
VIT–  
Vhys  
Positive-going input threshold voltage  
2.10  
1.10  
V
Negative-going input threshold voltage  
1.65  
0.8  
V
Input voltage hysteresis (VIT+ – VIT–  
)
1.0  
For pullup: VIN = VSS  
For pulldown: VIN = VCC  
RPull  
CI  
Pullup or pulldown resistor  
Input capacitance  
20  
35  
5
50  
kΩ  
VIN = VSS or VCC  
pF  
(1)  
Inputs – Ports P1 and P2  
(P1.0 to P1.7, P2.0 to P2.7)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
MAX UNIT  
(2)  
t(int)  
External interrupt timing  
External trigger pulse duration to set interrupt flag  
2 V, 3 V  
20  
ns  
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.  
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals  
shorter than t(int)  
.
Leakage Current – General Purpose I/O  
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
(1) (2)  
VCC  
MIN  
MAX UNIT  
50 nA  
Ilkg(Px.x)  
High-impedance leakage current  
2 V, 3 V  
-50  
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.  
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is  
disabled.  
Copyright © 2011–2012, Texas Instruments Incorporated  
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