MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
(1) (2) (3)
over recommended operating free-air temperature (unless otherwise noted)
(4)
Frequency (fMCLK = fSMCLK
)
EXECUTION
MEMORY
(5)
(5)
(5)
PARAMETER
VCC
1 MHz
TYP MAX
0.27
4 MHz
TYP MAX
0.58
8 MHz
TYP MAX
1.0
16 MHz
TYP MAX
1.53
20 MHz
TYP MAX
1.9
24 MHz
TYP
UNIT
MAX
(6)
IAM, FRAM_UNI
FRAM
3 V
3 V
2.2
mA
mA
mA
FRAM
0% cache hit
ratio
(7)
IAM,0%
0.42
0.31
0.27
0.25
0.73
1.2
0.73
0.58
0.5
1.6
2.2
1.3
2.8
2.3
1.75
1.55
1.3
2.9
2.8
2.1
1.9
1.6
3.6
3.45
4.3
FRAM
50% cache hit
ratio
(7) (8)
IAM,50%
3 V
3 V
3 V
2.5
2.2
1.8
FRAM
66% cache hit
ratio
(7) (8)
IAM,66%
1.0
FRAM
75% cache hit
ratio
(7) (8)
IAM,75%
0.82
FRAM
100% cache hit
ratio
(7) (8)
IAM,100%
3 V
3 V
0.2
0.2
0.43
0.4
0.3
0.55
0.55
0.42
0.55
0.8
0.73
1.0
1.15
1.25
0.88
1.20
1.3
1.0
1.5
(8) (9)
IAM, RAM
RAM
0.35
0.75
1.45
1.45
1.75
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Characterized with program executing typical data processing.
(4) At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency,
fMCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the number of
wait states or the cache hit ratio. The following equation can be used to compute fMCLK,eff:
fMCLK,eff,MHZ= fMCLK,MHZ x 1 / [# of wait states x ((1 - cache hit ratio percent/100)) + 1]
(5) MSP430FR573x series only
(6) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
(7) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz).MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz).MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz).MCLK = SMCLK. Three wait states enabled.
(8) See Figure 1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Active Mode Supply Current Into VCC Excluding External Current.
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(9) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz). MCLK = SMCLK.
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