MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
(1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
–0.3 V to VCC + 0.3 V
±2 mA
(2)
Voltage applied to any pin (excluding VCORE)
Diode current at any device pin
(3) (4) (5)
Storage temperature range, Tstg
-55°C to 125°C
95°C
Maximum junction temperature, TJ
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg
.
(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
Recommended Operating Conditions
MIN NOM
MAX UNIT
(1)
VCC
VSS
TA
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
Supply voltage (AVSS = DVSS)
2.0
3.6
V
V
0
Operating free-air temperature
Operating junction temperature
Required capacitor at VCORE
I version
I version
-40
-40
470
85
85
°C
°C
nF
TJ
CVCORE
CVCC
CVCORE
/
Capacitor ratio of VCC to VCORE
10
0
(3)
No FRAM wait states
2 V ≤ VCC ≤ 3.6 V
,
8.0
(3)
(2)
With FRAM wait states
NACCESS = {2},
NPRECHG = {1},
2 V ≤ VCC ≤ 3.6 V
,
fSYSTEM
Processor frequency (maximum MCLK frequency)
MHz
0
24.0
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(3) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
Copyright © 2011–2012, Texas Instruments Incorporated
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