欢迎访问ic37.com |
会员登录 免费注册
发布采购

MSP430FR5732IRGER 参数 Datasheet PDF下载

MSP430FR5732IRGER图片预览
型号: MSP430FR5732IRGER
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 109 页 / 1238 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号MSP430FR5732IRGER的Datasheet PDF文件第46页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第47页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第48页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第49页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第51页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第52页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第53页浏览型号MSP430FR5732IRGER的Datasheet PDF文件第54页  
MSP430FR573x  
MSP430FR572x  
SLAS639D JULY 2011REVISED AUGUST 2012  
www.ti.com  
Outputs – General Purpose I/O  
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
VCC – 0.25  
VCC – 0.60  
VCC – 0.25  
VCC – 0.60  
MAX UNIT  
(1)  
I(OHmax) = –1 mA  
VCC  
2 V  
(2)  
(1)  
(2)  
I(OHmax) = –3 mA  
I(OHmax) = –2 mA  
I(OHmax) = –6 mA  
VCC  
VOH  
High-level output voltage  
V
VCC  
3 V  
2 V  
3 V  
VCC  
(1)  
I(OLmax) = 1 mA  
I(OLmax) = 3 mA  
I(OLmax) = 2 mA  
I(OLmax) = 6 mA  
VSS VSS + 0.25  
(2)  
VSS VSS + 0.60  
VSS VSS + 0.25  
VSS VSS + 0.60  
VOL  
Low-level output voltage  
V
(1)  
(2)  
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop  
specified.  
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage  
drop specified.  
Output Frequency – General Purpose I/O  
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
2 V  
3 V  
2 V  
3 V  
MIN  
MAX UNIT  
16  
Port output frequency  
(with load)  
(1) (2)  
fPx.y  
Px.y  
MHz  
24  
16  
ACLK, SMCLK, or MCLK at configured output port,  
fPort_CLK  
Clock output frequency  
MHz  
24  
(2)  
CL = 20 pF, no DC loading  
(1) A resistive divider with 2 × 1.6 kbetween VCC and VSS is used as load. The output is connected to the center tap of the divider.  
CL = 20 pF is connected from the output to VSS  
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.  
.
50  
Submit Documentation Feedback  
Copyright © 2011–2012, Texas Instruments Incorporated  
 复制成功!