MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Table 40. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
Table 41. ADC10_B Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_B Control register 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_B Control register 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_B Control register 2
ADC10_B Window Comparator Low Threshold
ADC10_B Window Comparator High Threshold
ADC10_B Memory Control Register 0
ADC10_B Conversion Memory Register
ADC10_B Interrupt Enable
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10_B Interrupt Flags
ADC10IGH
ADC10IV
ADC10_B Interrupt Vector Word
Table 42. Comparator_D Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
Comparator_D control register 0
REGISTER
CDCTL0
OFFSET
00h
02h
04h
06h
0Ch
0Eh
Comparator_D control register 1
Comparator_D control register 2
Comparator_D control register 3
Comparator_D interrupt register
Comparator_D interrupt vector word
CDCTL1
CDCTL2
CDCTL3
CDINT
CDIV
44
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