MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
SD24_B, Power Supply and Recommended Operating Conditions
MIN
2.4
TYP
MAX UNIT
AVCC
fSD
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
3.6
2.3
V
MHz
V
Modulator clock frequency(1)
Absolute input voltage range
Common-mode input voltage range
Differential full scale input voltage
0.03
VI
AVSS - 1V
AVSS - 1V
-VREF/GAIN
±910
AVCC
VIC
AVCC
V
VID,FS
VID = VI,A+ - VI,A-
SD24GAINx = 1
SD24GAINx = 2
SD24GAINx = 4
SD24GAINx = 8
+VREF/GAIN
±920
±460
±230
±115
±58
±455
±227
±113
mV
nF
Differential input voltage for specified
performance(2)
VID
SD24REFS = 1
SD24GAINx = 16
SD24GAINx = 32
SD24GAINx = 64
±57
±28
±29
±14
±14.5
SD24GAINx =
128
±7
±7.2
100
CREF
VREF load capacitance(3)
SD24REFS = 1
(1) Modulator clock frequency: MIN = 32.768 kHz - 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
(2) The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS-= -VREF/GAIN: FSR = VFS+ - VFS-= 2*VREF/GAIN. If VREF is sourced
externally, the analog input range should not exceed 80% of VFS+ or VFS-; i.e., VID = 0.8 VFS- to 0.8 VFS+. If VREF is sourced internally,
the given VID ranges apply.
(3) There is no capacitance required on VREF. However, a capacitance of 100nF is recommended to reduce any reference voltage noise.
(1)
SD24_B, Analog Input
PARAMETER
TEST CONDITIONS
SD24GAINx = 1
VCC
MIN
TYP
5
MAX UNIT
SD24GAINx = 2
5
SD24GAINx = 4
5
CI
Input capacitance
pF
SD24GAINx = 8
5
SD24GAINx = 16
SD24GAINx = 32, 64, 128
5
5
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
SD24GAINx = 1
SD24GAINx = 8
SD24GAINx = 32
3 V
3 V
3 V
3 V
3 V
3 V
200
200
200
400
400
400
Input impedance
(Pin A+ or A- to AVSS
ZI
fSD24 = 1MHz
fSD24 = 1MHz
kΩ
kΩ
)
300
300
Differential input impedance
(Pin A+ to pin A-)
ZID
(1) All parameters pertain to each SD24_B converter.
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