MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
4
TYP
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
3
0
STE lag time, Last clock to STE inactive
ns
0
46
ns
24
STE access time, STE active to SOMI data out
38
ns
25
STE disable time, STE inactive to SOMI high
impedance
2
1
2
2
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
ns
tHD,SI
55
ns
32
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
24
16
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams
inFigure 15 and Figure 16.
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 15. SPI Slave Mode, CKPH = 0
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