MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
SD24_B, Performance (continued)
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFS = 1
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
-1
TYP
MAX UNIT
SD24GAIN: 1, with external reference (1.2 V)
SD24GAIN: 8, with external reference (1.2 V)
SD24GAIN: 32, with external reference (1.2 V)
+1
EG
Gain error(1)
-2
+2
+2
%
-2
Gain error temperature
coefficient(2), internal
reference
ΔEG/ΔT
ΔEG/ΔVCC
SD24GAIN: 1/8/32 (with internal reference)
3 V
50 ppm/°C
SD24GAIN: 1
0.15
0.15
0.4
(3)
Gain error vs VCC
SD24GAIN: 8
%/V
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0V)
SD24GAIN: 8
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
3 V
2.3
0.73
EOS[V]
Offset error(4)
Offset error(4)
mV
SD24GAIN: 32
SD24GAIN: 1 (with Vdiff = 0V)
SD24GAIN: 8
0.18
0.2
-0.2
-0.5
-0.5
EOS[FS]
0.5 % FS
0.5
SD24GAIN: 32
SD24GAIN: 1
1
0.15
0.1
Offset error temperature
coefficient(5)
ΔEOS/ΔT
ΔEOS/ΔVCC
CMRR,DC
SD24GAIN: 8
uV/°C
uV/V
dB
SD24GAIN: 32
SD24GAIN: 1
600
100
50
(6)
Offset error vs VCC
SD24GAIN: 8
SD24GAIN: 32
SD24GAIN: 1
3 V
3 V
3 V
-110
-110
-110
Common mode rejection
at DC(7)
SD24GAIN: 8
SD24GAIN: 32
(1) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact - Gnom)/Gnom. It covers process,
temperature and supply voltage variations.
(2) The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) -
Gnom)/Gnom) using the box method (i.e. min. and max. values):
ΔEG/ ΔT = (MAX(EG(T)) - MIN(EG(T) ) / (MAX(T) - MIN(T)) = (MAX(Gact(T)) - MIN(Gact(T)) / Gnom / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
(3) The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) -
Gnom)/Gnom) using the box method (i.e. min. and max. values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) - MIN(EG(VCC) ) / (MAX(VCC) - MIN(VCC)) = (MAX(Gact(VCC)) - MIN(Gact(VCC)) / Gnom / (MAX(VCC) -
MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
(4) The offset error EOS is measured with shorted inputs in 2's complement mode with +100% FS = VREF/G and -100% FS = -VREF/G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V]×G/VREF; EOS [V] = EOS [FS]×VREF/G.
(5) The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method
(i.e. min. and max. values):
ΔEOS/ ΔT = (MAX(EOS(T)) - MIN(EOS(T) ) / (MAX(T) - MIN(T))
with T ranging from -40°C to +85°C.
(6) The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (i.e. min.
and max. values):
ΔEOS/ ΔVCC = (MAX(EOS(VCC)) - MIN(EOS(VCC) ) / (MAX(VCC) - MIN(VCC))
with VCC ranging from 2.4V to 3.6V.
(7) The DC CMRR specifies the change in the measured differential input voltage value when the common mode voltage varies:
DC CMRR = -20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when
sweeping the common mode voltage (for example, calculating with 16-bits FSR = 65536 a maximum change by 1 LSB results in -
20log(1/65536) ≈ -96 dB) .
The DC CMRR is measured with both inputs connected to the common mode voltage (i.e. no differential input signal is applied), and the
common mode voltage is swept from -1V to VCC
.
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