MSP430F673x
MSP430F672x
www.ti.com
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
eUSCI (SPI Master Mode) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
0
TYP
MAX UNIT
2.0 V
3.0 V
2.0 V
3.0 V
2.0 V
3.0 V
SOMI input data hold
time
tHD,MI
ns
0
9
SIMO output data valid
time(2)
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
CL = 20 pF
ns
5
0
0
SIMO output data hold
time(3)
tHD,MO
ns
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 15 and Figure 16.
UCMODEx = 01
tSTE,LEAD
tSTE,LAG
STE
UCMODEx = 10
CKPL = 0
1/fUCxCLK
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 13. SPI Master Mode, CKPH = 0
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
65
TI [ TEXAS INSTRUMENTS ]
