MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
1.8 V/
3.0 V
fTA
Timer_A input clock frequency
25 MHz
All capture inputs.
Minimum pulse width required for
capture.
1.8 V/
3.0 V
tTA,cap
Timer_A capture timing
20
ns
eUSCI (UART Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
5
MHz
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
10
TYP
15
MAX UNIT
25
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
30
50
85
ns
2.0 V/3.0
V
tt
UART receive deglitch time(1)
50
80
150
70
120
200
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
eUSCI (SPI Master Mode) - Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2.0 V/3.0 V
2.0 V/3.0 V
2.0 V/3.0 V
2.0 V/3.0 V
2.0 V
MIN
150
150
200
200
TYP
MAX UNIT
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
STE lead time, STE
active to clock
tSTE,LEAD
ns
STE lag time, Last clock
to STE inactive
tSTE,LAG
ns
50
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 0, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
3.0 V
30
ns
50
STE access time, STE
active to SIMO data out
tSTE,ACC
2.0 V
3.0 V
30
40
2.0 V
STE disable time, STE
inactive to SIMO high
impedance
3.0 V
25
ns
40
tSTE,DIS
2.0 V
3.0 V
25
2.0 V
50
30
SOMI input data setup
time
tSU,MI
ns
3.0 V
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
64
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