MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC to DVSS
-0.3 V to 4.1 V
-0.3 V to VCC + 0.3 V
±2 mA
Voltage applied to any pin (excluding VCORE)(2)
Diode current at any device pin
(3)
Storage temperature range, Tstg
–55°C to 150°C
95°C
Maximum junction temperature, TJ
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Recommended Operating Conditions
MIN NOM
MAX UNIT
PMMCOREVx = 0
1.8
2.0
2.2
2.4
0
3.6
3.6
3.6
3.6
V
V
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
Supply voltage during program execution and flash
programming. V(AVCC) = V(DVCC) = VCC
VCC
(1)
V
V
VSS
TA
Supply voltage V(AVSS) = V(DVSS) = VSS
Operating free-air temperature
V
I version
I version
–40
–40
470
85
85
°C
°C
nF
TJ
Operating junction temperature
CVCORE
Recommended capacitor at VCORE
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(2)(3)
(see Figure 1)
0
0
0
12.0
20.0
fSYSTEM
MHz
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
25.0
20
20
20
10
5
ILOAD,
DVCCD
ILOAD,
AUX1D
ILOAD,
AUX2D
ILOAD,
AVCCA
ILOAD,
AUX1A
ILOAD,
AUX2A
Maximum load current that can be drawn from DVCC for
mA
mA
mA
mA
mA
mA
core and IO (ILOAD = ICORE + IIO
Maximum load current that can be drawn from AUXVCC1 for
core and IO (ILOAD = ICORE + IIO
Maximum load current that can be drawn from AUXVCC2 for
core and IO (ILOAD = ICORE + IIO
Maximum load current that can be drawn from AVCC for
analog modules (ILOAD = IModules
Maximum load current that can be drawn from AUXVCC1 for
analog modules (ILOAD = IModules
Maximum load current that can be drawn from AUXVCC2 for
analog modules (ILOAD = IModules
)
)
)
)
)
5
)
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC)
can be tolerated during power up and operation.
(2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(3) Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.
Copyright © 2011–2012, Texas Instruments Incorporated
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