MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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Table 56. eUSCI_A1 Registers (Base Address:05E0h) (continued)
REGISTER DESCRIPTION
REGISTER
UCA1IFG
OFFSET
eUSCI_A interrupt flags
1Ch
1Eh
eUSCI_A interrupt vector word
UCA1IV
Table 57. eUSCI_A2 Registers (Base Address:0600h)
REGISTER DESCRIPTION
REGISTER
UCA2CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA2CTLW1
UCA2BR0
eUSCI_A baud rate 1
UCA2BR1
eUSCI_A modulation control
eUSCI_A status
UCA2MCTLW
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA2IFG
UCA2IV
Table 58. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
44
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