MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Table 53. DMA Channel 1 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA1CTL
OFFSET
OFFSET
OFFSET
DMA channel 1 control
20h
22h
24h
26h
28h
2Ah
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
Table 54. DMA Channel 2 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
DMA2CTL
DMA channel 2 control
30h
32h
34h
36h
38h
3Ah
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
Table 55. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
eUSCI_A baud rate 1
eUSCI_A modulation control
eUSCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA0IFG
eUSCI_A interrupt vector word
UCA0IV
Table 56. eUSCI_A1 Registers (Base Address:05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
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