MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
www.ti.com
Table 15. Default Mapping
PIN NAME
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PZ
PN
P1.0/PM_TA0.0/
VeREF-/A2
P1.0/PM_TA0.0/
VeREF-/A2
PM_TA0.0
PM_TA0.1
TA0 CCR0 capture input CCI0A
TA0 CCR1 capture input CCI1A
TA0 CCR0 compare output Out0
TA0 CCR1 compare output Out1
P1.1/PM_TA0.1/
VeREF+/A1
P1.1/PM_TA0.1/
VeREF+/A1
eUSCI_A0 UART RXD
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A0
PM_UCA0RXD,
PM_UCA0SOMI
(direction controlled by eUSCI – input),
eUSCI_A0 SPI slave out master in
(direction controlled by eUSCI)
eUSCI_A0 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A0 SPI slave in master out
(direction controlled by eUSCI)
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
P1.3/PM_UCA0TXD/
PM_UCA0SIMO/R03
PM_UCA0TXD,
PM_UCA0SIMO
eUSCI_A1 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A1 SPI slave out master in
(direction controlled by eUSCI)
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
P1.4/PM_UCA1RXD/
PM_UCA1SOMI/
LCDREF/R13
PM_UCA1RXD,
PM_UCA1SOMI
eUSCI_A1 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A1 SPI slave in master out
(direction controlled by eUSCI)
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
P1.5/PM_UCA1TXD/
PM_UCA1SIMO/R23
PM_UCA1TXD,
PM_UCA1SIMO
P1.6/PM_UCA0CLK/
COM4
P1.6/PM_UCA0CLK/
COM4
PM_UCA0CLK
PM_UCB0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
eUSCI_B0 clock input/output (direction controlled by eUSCI)
P1.7/PM_UCB0CLK/
COM5
P1.7/PM_UCB0CLK/
COM5
eUSCI_B0 SPI slave out master in
(direction controlled by eUSCI),
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6
P2.0/PM_UCB0SOMI/
PM_UCB0SCL/COM6/S39
PM_UCB0SOMI,
PM_UCB0SCL
eUSCI_B0 I2C clock
(open drain and direction controlled by eUSCI)
eUSCI_B0 SPI slave in master out
(direction controlled by eUSCI),
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7
P2.1/PM_UCB0SIMO/
PM_UCB0SDA/COM7/S38
PM_UCB0SIMO,
PM_UCB0SDA
eUSCI_B0 I2C data
(open drain and direction controlled by eUSCI)
eUSCI_A2 UART RXD
(direction controlled by eUSCI – input),
eUSCI_A2 SPI slave out master in
(direction controlled by eUSCI)
P2.2/PM_UCA2RXD/
PM_UCA2SOMI
P2.2/PM_UCA2RXD/
PM_UCA2SOMI/S37
PM_UCA2RXD,
PM_UCA2SOMI
eUSCI_A2 UART TXD
(direction controlled by eUSCI – output),
eUSCI_A2 SPI slave in master out
(direction controlled by eUSCI)
P2.3/PM_UCA2TXD/
PM_UCA2SIMO
P2.3/PM_UCA2TXD/
PM_UCA2SIMO/S36
PM_UCA2TXD,
PM_UCA2SIMO
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
P2.6/PM_TA1.0
P2.7/PM_TA1.1
P3.0/PM_TA2.0
P3.1/PM_TA2.1
P2.4/PM_UCA1CLK/S35
P2.5/PM_UCA2CLK/S34
P2.6/PM_TA1.0/S33
P2.7/PM_TA1.1/S32
P3.0/PM_TA2.0/S31
P3.1/PM_TA2.1/S30
PM_UCA1CLK
PM_UCA2CLK
PM_TA1.0
eUSCI_A1 clock input/output (direction controlled by eUSCI)
eUSCI_A2 clock input/output (direction controlled by eUSCI)
TA1 CCR0 capture input CCI0A
TA1 CCR1 capture input CCI1A
TA2 CCR0 capture input CCI0A
TA2 CCR1 capture input CCI1A
TA1 CCR0 compare output Out0
TA1 CCR1 compare output Out1
TA2 CCR0 compare output Out0
TA2 CCR1 compare output Out1
PM_TA1.1
PM_TA2.0
PM_TA2.1
P3.2/PM_TACLK/
PM_RTCCLK
P3.2/PM_TACLK/
PM_RTCCLK/S29
PM_TACLK,
PM_RTCCLK
Timer_A clock input to
TA0, TA1, TA2, TA3
RTC_C clock output
P3.3/PM_TA0.2
P3.3/PM_TA0.2/S28
P3.4/PM_SDCLK/S27
PM_TA0.2
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
SD24_B bit stream clock input/output
(direction controlled by SD24_B)
P3.4/PM_SDCLK/S39
PM_SDCLK
SD24_B converter-0 bit stream data input/output
(direction controlled by SD24_B)
P3.5/PM_SD0DIO/S38
P3.6/PM_SD1DIO/S37
P3.7/PM_SD2DIO/S36
P3.5/PM_SD0DIO/S26
P3.6/PM_SD1DIO/S25
P3.7/PM_SD2DIO/S24
PM_SD0DIO
PM_SD1DIO
PM_SD2DIO
SD24_B converter-1 bit stream data input/output
(direction controlled by SD24_B)
SD24_B converter-2 bit stream data input/output
(direction controlled by SD24_B)
28
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
