MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Auxiliary Supply System
The auxiliary supply system provides the possibility to operate the device from auxiliary supplies when the
primary supply fails.There are two auxililary supplies AUXVCC1 and AUXVCC2 supported in MSP430F67xx.
This module supports automatic and manual switching from primary supply to auxiliary suppllies while
maintaining full functionality. It allows threshold based monitoring of primary and auxiliary supplies. The device
can be started from primary supply or AUXVCC1, whichever is higher. Auxiliary supply system enables internal
monitoring of voltage levels on primary and auxiliary supplies using ADC10_A. Also this module implements
simple charger for backup supplies.
Backup Subsystem
The Backup subsystem operates on a dedicated power supply AUXVCC3. This subsystem includes low-
frequency oscillator (XT1), Real-Time Clock module, and Backup RAM. The functionality of Backup subsystem is
retained during LPM3.5. The Backup susb-system module registers can not be accessed by CPU when the high
side SVS is disabled by user. It is necessary to keep the high side SVS enabled with SVSHMD = 1 and
SVSMHACE = 0 to turn off the low-frequency oscillator (XT1) in LPM4.
Digital I/O
There are up to nine 8-bit I/O ports implemented. For 100 pin options, Ports P1 to P8 are complete. P9 is
reduced to 4-bit I/O. For 80 pin options, Ports P1 to P6 are complete. P7, P8 and P9 are completely removed.
Port PJ contains four individual I/O pins, common to all devices. All I/O bits are individually programmable.
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Any combination of input, output and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Programmable drive strength on all ports.
Edge-selectable interrupt and LPM3.5, LPM4.5 wakeup input capability available for all bits of ports P1 and
P2.
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Read-write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PE).
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