MSP430F663x
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SLAS566C –JUNE 2010–REVISED AUGUST 2012
Recommended Operating Conditions (continued)
MIN NOM
MAX UNIT
CVCORE
CDVCC
CVCORE
Capacitor at VCORE
470
nF
/
Capacitor ratio of DVCC to VCORE
10
0
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
8.0
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency)(4)(5)
(see Figure 1)
0
0
0
12.0
MHz
fSYSTEM
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V
16.0
20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V
fSYSTEM_USB
USB_wait
Minimum processor frequency for USB operation
Wait state cycles during USB operation
1.5
MHz
16
cycles
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
20
3
16
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Frequency vs Supply Voltage
Copyright © 2010–2012, Texas Instruments Incorporated
47
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