MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
–0.3 V to VCC + 0.3 V
±2 mA
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)
Diode current at any device pin
(3)
Storage temperature range, Tstg
–55°C to 150°C
95°C
Maximum junction temperature, TJ
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics
PARAMETER
VALUE
122
108
83
UNIT
QFP (PZ)
θJA
Junction-to-ambient thermal resistance, still air(1)
°C/W
BGA (ZQW)
QFP (PZ)
θJC(TOP)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
°C/W
°C/W
BGA (ZQW)
QFP (PZ)
72
98
θJB
BGA (ZQW)
76
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Recommended Operating Conditions
MIN NOM
MAX UNIT
PMMCOREVx = 0
1.8
2.0
2.2
2.4
1.8
2.0
2.2
2.4
2.2
2.4
3.6
Supply voltage during program execution and flash
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 0
3.6
V
VCC
programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =
(1)(2)
3.6
DVCC = VCC
)
3.6
3.6
3.6
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
PMMCOREVx = 2
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0)
3.6
V
VCC,USB
3.6
Supply voltage during USB operation, USB PLL enabled(3)
(USB_EN = 1, UPLLEN = 1)
3.6
3.6
PMMCOREVx = 2, 3
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =
VSS
0
V
DVSS2 = DVSS3 = VSS
)
TA = 0°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
I version
1.55
1.70
1.20
–40
3.6
V
VBAT,RTC
Backup-supply voltage with RTC operational
3.6
VBAT,MEM
TA
Backup-supply voltage with backup memory retained.
Operating free-air temperature
3.6
85
85
10
V
°C
°C
nF
TJ
Operating junction temperature
I version
–40
CBAK
Capacitance at pin VBAK
1
4.7
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
46
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