LMH0324
www.ti.com.cn
ZHCSIC8B –APRIL 2016–REVISED JUNE 2018
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS
2-Level Input (SS_N, SCK, MOSI),
VDDIO = 2.5 V or 1.8 V
0.7 x VDDIO
VDDIO + 0.3
3.6
VIH
High Level Input Voltage
V
2-Level Input (SCL, SDA), VDDIO
= 2.5 V
0.7 x VDDIO
2-Level Input (SS_N, SCK, MOSI)
VDDIO = 2.5 V or 1.8 V
-0.3
0.3 x VDDIO
0.3 x VDDIO
VDDIO
0.2 x VDDIO
0.4
VIL
Low Level Input Voltage
V
V
V
2-Level Input (SCL, SDA), VDDIO
= 2.5 V
0
High Level Output
Voltage
IOH = -2 mA, (MISO), VDDIO = 2.5
V or 1.8 V
VOH
0.8 x VDDIO
IOL = 2 mA, (MISO), VDDIO = 2.5
V or 1.8 V
0
0
Low Level Output
Voltage
VOL
IOL = 3 mA, (CD_N, SCL, SDA),
VDDIO = 2.5 V
SPI Mode: LVCMOS (SS_N, SCK,
MOSI), Vinput = VDDIO
15
Input High Leakage
Current
IIH
µA
µA
SMBus Mode: LVCMOS (CD_N,
SCL, SDA), Vinput = VDDIO
10
SPI Mode: LVCMOS (SS_N),
Vinput = VSS
-40
-15
-10
Input Low Leakage
Current
SPI Mode: LVCMOS (SCK,
MOSI), Vinput = VSS
IIL
SMBus Mode: LVCMOS (CD_N,
SCL, SDA), Vinput = VSS
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V4_LVL_H
V4_LVL_F
LEVEL-H Input Voltage
External pull-up 1 kΩ to VDDIO
VDDIO
V
V
LEVEL-F Default Voltage Float, VDDIO = 2.5 V or 1.8 V
2/3 x VDDIO
External pull-down 20 kΩ to VSS,
LEVEL-R Input Voltage
V4_LVL_R
V4_LVL_L
1/3 x VDDIO
0
V
V
VDDIO = 2.5 V or 1.8 V
LEVEL-L Input Voltage
External pull-down 1 kΩ to VSS
4-Levels (IN_OUT_SEL,
OUT_CTRL, VOD_DE,
MODE_SEL), Vinput = VDDIO
20
20
45
45
80
80
Input High Leakage
Current
I4_LVL_IH
µA
µA
SMBus Mode: 4-Levels (ADDR0,
ADDR1), Vinput = VDDIO
4-Levels (IN_OUT_SEL,
OUT_CTRL, VOD_DE,
MODE_SEL), Vinput = VSS
-160
-160
–93
–93
-40
-40
Input Low Leakage
Current
I4_LVL_IL
SMBus Mode: 4-Levels (ADDR0,
ADDR1), Vinput = VSS
RECEIVER SPECIFICATIONS (IN0+)
RIN0_TERM
DC Input Termination
IN0+ and IN0- to VSS
63
75
–20
–18
87
Ω
S11, 5 MHz to 1.485 GHz
S11, 1.485 GHz to 3 GHz
Input Return Loss
RLIN0
dB
Reference to 75 Ω(2)
IN0 DC Common Mode
Voltage
Input common mode voltage at
IN0+ to VSS
VIN0_CM
1.4
100
50
V
SD signal at IN0+, Input launch
amplitude = 0.8 Vp-p
mVp-p
mVp-p
VWANDER
Input DC Wander
HD, 3G signal at IN0+, Input
launch amplitude = 0.8 Vp-p
(2) This parameter was measured with an LMH0324-18EVM.
Copyright © 2016–2018, Texas Instruments Incorporated
7
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