HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Motherboard
PCI Device
PCI Bus
HOST/PCI
PCLK
PRST
SYSM66EN
PCI Bus Less PRST and REQ64
CBT–SW
8–BIT
PORT
BUSON
CLKON
INTR
CBT–SW
P
C
REQ64ON
I
CBT–SW
SLOTREQ64
S
HPC–PCI
L
O
T
M66EN
IDLEREQ
IDLEGNT
PRSNT(1–2)
SLOTRST
PWRON/OFF
PERFAULT
PWRGOOD
FRAME
IRDY
PWR–SW
DETECT(0–1)
ATTN(0–1)
Figure 1. HPC3130A Implementation
The HPC3130A internal registers can be accessed through either a two-wire serial interface or an 8-bit generic
parallel bus (ISA-like). The above figure illustrates the 8-bit port configuration. Not shown in the diagram is the
SMODE chip input that must be wired low to indicate parallel bus interface mode. Also not shown in the diagram
is the external chip-select logic required to select the HPC3130A in ISA bus cycles.
serial interface
The internal registers can be accessed either through a two-wire serial interface or through an 8-bit generic
parallel interface. The SMODE input selects one of these modes.
The HPC3130A implements a two-pin serial slave interface with one clock signal (SCL) and one data signal
(SDA). This serial interface can operate with a serial clock frequency up to 400 kHz. Both SCL and SDA require
pullup resistors for the serial slave interface to function properly.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a START
condition (S) when the SDA line transitions to a low state while SCL is in a high state as illustrated in Figure 2.
The end of a requested data transfer is indicated by a STOP condition (P), which is the low-to-high transition
of SDA while SCL is in the high state. Data on SDA must remain stable during the high state of the SCL signal.
Changes on the SDA signal during the high state of SCL will be interpreted as control signals, that is, a START
or STOP condition.
The SCL is an input into the HPC3130A and SDA is bidirectional.
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