HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Terminal Functions
This section describes the HPC3130A terminal functions. The terminals are grouped in tables by function.
power supply terminal functions
TERMINAL
NO.
120
NO.
128
NO.
144
I/O
FUNCTION
Device ground terminals
NAME
GND
11, 17, 26, 41, 51,
12, 18, 27, 44, 54,
14, 20, 29, 50, 60,
I
68, 79, 101, 112, 117 73, 84, 108, 119, 124 83, 94, 122, 133, 138
V
V
V
6, 36, 56, 85, 95
15, 28, 46, 74, 107
22
7, 39, 59, 90, 102
16, 29, 49, 79, 114
23
9, 45, 65, 100, 116
18, 32, 55, 89, 128
25
I
I
I
3.3-V power supply
CC
5-V clamp-rail voltage supply
CC5V
CCP
Clamp rail voltage for PCI signaling (5V or 3.3V)
control bus interface
TERMINAL
NO.
120
NO.
128
NO.
144
I/O
FUNCTION
NAME
Parallel bus address. These terminals are address inputs in generic parallel bus cycles and are
only used when the SMODE is input low. These lower address terminals select one of the eight
registers for read/write access.
A2/ADD2
A1/ADD1
A0/ADD0
48
49
50
51
52
53
57
58
59
I
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Parallel bus address. These terminals are address inputs in generic parallel bus cycles, and are
only used when SMODE is input low. These upper address terminals select one of four hot-plug
slots supported by the HPC3130A.
A4/ADD4
A3/ADD3
45
47
48
50
54
56
I
I
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A
when the SMODE is input high.
Chip selection. This active low input selects the HPC3130A chip as addressed in the current
generic parallel bus cycle. This chip input is only valid if the SMODE is input low. Multiple
HPC3130A chips may exist in a system with external logic driving this signal.
CS
34
37
43
Parallelbus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
DATA1/ADD6
DATA0/ADD5
43
44
46
47
52
53
I/O
Serial bus address selection. These terminals indicate the full serial bus address of the
HPC3130A when the SMODE is input high.
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
35
37
38
39
40
42
38
40
41
42
43
45
44
46
47
48
49
51
Parallelbus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
I/O
Read selection. This terminal indicates a register read cycle when the SMODE input is low and
the CS terminal input is asserted. This is used to read an internal HPC3130A register.
RD/SDA
WR/SCL
29
30
30
31
34
36
I/O
Serialbusdata. ThisterminalsignalstheserialbusdatawhentheSMODEinputishigh. Itisused
during internal register read and write transactions.
Write selection. This terminal indicates a register write cycle when the SMODE input is low and
the CS terminal input is asserted. This input is used to write to an internal HPC3130A register.
I
Serial bus clock. This terminal inputs serial bus clock in when the SMODE input is high. It is used
during internal register read and write transactions.
12
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