HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
connection sequencing (continued)
If automatic sequencing mode 1 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch–timing block will arbitrate for the PCI bus by asserting IDLEREQ.
Subsequently, IDLEGNT is asserted and the HPC3130A waits for bus idle condition. When FRAME and IRDY
are deasserted, the CBT switches are enabled. Following this, the SLOTRST, SLOTREQ64 and REQ64ON are
deasserted. Figure 7 depicts the sequencing of events when automatic sequencing mode 1 is enabled.
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
IDLEGNT
FRAME
IRDY
BUSON
Figure 7. Automatic Connection Sequencing Mode 1
If automatic sequencing mode 2 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch timing block arbitrates for the PCI bus by asserting IDLEREQ.
Subsequently, IDLEGNT is asserted and the HPC3130A waits for the bus idle condition. When FRAME and
IRDY are deasserted, the SLOTRST is deasserted. Following this, the SLOTREQ64 and REQ64ON are
deasserted and the CBT switches are enabled. Figure 8 depicts the sequencing of events when automatic
sequencing mode 2 is enabled.
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