HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
Terminal Functions (Continued)
system interface
TERMINAL
NO.
120
NO.
128
NO.
144
I/O
FUNCTION
NAME
Frame. This input and the IRDY input indicate that the PCI bus is idle. When the HPC3130A
senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot can be connected to the PCI
bus. Thisinputmustbewiredtoavalidlogiclevelifthebusidlingprocedureisnotimplemented.
FRAME
20
19
18
21
23
22
21
I
I
Idle grant. This input indicates when the PCI bus is idled by the HOST-PCI bridge after a
requestismadebyIDLEREQ. TheprotocolisidenticaltoPCIrequest/grant. Thisinputmustbe
wired to a valid logic level if the bus idling procedure is not implemented.
IDLEGNT
IDLEREQ
20
19
Idle request. This output is driven to request the HOST-PCI bridge to idle the PCI bus before
connectinga hot-plug slot. The protocol is identical to PCI request/grant. A pullup resistor must
be implemented on this terminal if the bus idling procedure is not implemented.
O
Systeminterrupt. Thisoutputprovidesasysteminterrupt. TheHPC3130Acanbeprogrammed
toassertthisinterruptundervariousconditions, whichmaybeservicedbythehot-plugservice.
Furthermore, the event status/enable state is compliant with the ACPI Specification and, as a
result, supports ACPI control methods for switching the HPC3130A.
INTR
INTR
24
23
25
24
27
26
O
O
System interrupt. This open drain output provides a system interrupt. The HPC3130A can be
programmed to assert this interrupt under various conditions, which may be serviced by the
hot-plug. Furthermore, the event status/enable state is compliant with the ACPI Specification
and, as a result, supports ACPI control methods for switching the HPC3130A.
Initiatorready. ThisandtheFRAMEinputindicatethatthePCIbusisidle.WhentheHPC3130A
senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot may be connected to the PCI
bus. Thisinputmustbewiredtoavalidlogiclevelifthebusidlingprocedureisnotimplemented.
IRDY
PCLK
PRST
21
16
14
22
17
15
24
19
17
I
I
I
PCI clock input. These terminals provide the PCI clock to the HPC3130A, which uses it only for
activity indicator timing, IDLEREQ/IDLEGNT protocol, and connection sequencing.
PCI reset. This signal provides the PCI reset to the HPC3130A. After a PCI reset, the
HPC3130A resides in a state where all slots are enabled, as in a non-hot-plug system. The
HPC3130A passes PCI resets from the host to all hot-plug slots.
Secondarygrant. ThisoutputprovidesaschemetocascadeasecondaryHPC3130Adevicein
order to provide more than four slots. The SGNT output from the primary HPC3130A is input to
theIDLEGNTterminalforthesecondaryHPC3130A.AfterthesecondaryHPC3130Arequests
the primary HPC3130A to idle the bus, the primary HPC3130A arbitrates for the bus using
IDLEREQ. Once IDLEGNT is asserted, the primary HPC3130A asserts its SGNT output. This
indicates to the secondary HPC3130A device that it can connect to the bus.
SGNT
13
14
16
O
Serial bus mode. When this input is asserted high, the internal HPC3130A registers are
accessible through the serial bus interface; otherwise, they are accessed through the generic
parallel bus interface. This input selects the control bus interface.
SMODE
SREQ
27
12
25
28
13
26
30
15
28
I
I
Secondary request. This input provides a scheme to cascade a second HPC3130A device in
order to provide more than four slots. The IDLEREQ from the second HPC3130A device is
input to the SREQ terminal of the primary HPC3130A. If the second HPC3130A device
arbitrates for the bus by asserting its IDLEREQ output, this scheme causes the primary
HPC3130A to assert its IDLEREQ. If cascading is not used, this input is pulled high.
PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the
hot-plug slots, and must be tied to the system PCI bus M66EN signal. The output from this
terminal only changes state after a PCI reset and is only required in a 66-MHz system.
SYSM66EN
I/O
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
