GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
4.1
MODE CONTROL REGISTER
This register contains the mode control bits. The suggested default value is 5280 (HEX).
ADDRESS 0:
MODE_REG
BIT
TYPE
NAME
DESCRIPTION
0,1 (LSBs)
R/W
INPUT[0:1]
This two bit field controls the input data selection. The
input modes are:
INPUT
DESCRIPTION
0
1
2
3
Complex data input
High speed real data input
Diagnostic ramp input
Zero input
2-6
7
R/W
R/W
-
unused
MIXER_ROUND
Round the mixer multiplier products to 12 bits. The
products are truncated to 12 bits if this control is low.
8
R/W
ADDER_CLEAR
Clears one input to the adder in the mixer circuit to allow
the Ieven and Qeven outputs to be routed to the symbol
offset circuitry. See Section 2.5.
9
R/W
R/W
2X_GAIN
OFFSET
Enables the 2X gain circuit in the mixer circuit.
10
Delays the I sample in the symbol offset circuit by one
clock cycle relative to the Q sample.
11
12
R/W
OFFSET_HOLD
Samples and holds every other I,Q pair in the symbol
offset circuit. The OFFSET_SYNC mode (See Section
4.2) determines how the sample and hold timing is
synchronized to the input data.
R/W
QMAP_ENABLE
Enables the quadrant map mode. This mode maps the
I,Q pairs into the first quadrant for phase error lookup
when this mode is selected. The error is then mapped
back to the correct quadrant after it is looked up in the
phase error memory.
13
R/W
QMAP_ROUND
Round instead of truncate the I,Q samples in the phase
error circuit. If QMAP_ENABLE is set the values are
rounded into the 7 MSBs, otherwise they are rounded to
the 6 MSB.
14
15
R/W
R/W
QMAP_INVERT
NCO_MODE
Convert negative numbers to positive numbers in the
Qmap mode by inverting the data bits (1’s complement
negation) rather than negating them.
Turns on the high speed NCO mode. Must be high for
the high speed double rate input mode, low otherwise.
Texas Instruments Incorporated
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