GC3021A 3.3V MIXER AND CARRIER REMOVAL CHIP
SLWS137A
The suggested default value for SYNC_REG1 is 7DF7 (HEX) which is to always sync AB_SYNC,
FREQ_SYNC and DITHER_SYNC (turns dithering off) and to sync PLL_SYNC and NCO_SYNC with the
oneshot strobe.
ADDRESS 2:
SYNC_REG1
NAME
BIT
TYPE
DESCRIPTION
0-2 (LSBs)
R/W
AB_SYNC
The PLL circuit accepts new A and B values when the
sync is asserted.
3-5
6-8
R/W
R/W
PLL_SYNC
The PLL accumulator is cleared by this sync.
FREQ_SYNC
The PLL accepts the new FREQ value from the FREQ
registers when this sync is asserted.
9-11
R/W
R/W
R/W
NCO_SYNC
The NCO accumulator is cleared by this sync.
The dither value circuit is cleared by this sync.
unused
12-14
DITHER_SYNC
-
15 (MSB)
4.3
DELAY CONTROL REGISTER
The DSA and DSB syncs are generated by delaying the SA and SB sync inputs by (2+DELAY)
clocks where DELAY ranges from 0 to 255. The suggested default is zero.
ADDRESS 3:
DELAY_REG
NAME
BIT
TYPE
DESCRIPTION
0-7 (LSBs)
R/W
DELAY_A
DELAY_B
The DELAY value for DSA.
The DELAY value for DSB.
8-15 (MSBs) R/W
4.4
COUNTER CONTROL REGISTER
The internal counter counts in cycles of 16*(COUNT+1) clocks by counting down from
(16*COUNT+15) to zero and starting over again. The counter emits a terminal count (TC) each time it
reaches zero. The suggested default is 00FF (HEX) which sets a counter cycle of 4096.
ADDRESS 4:
COUNT_REG
BIT
TYPE
NAME
COUNT
DESCRIPTION
0-15
R/W
The counter period is 16*(COUNT+1) clocks.
Texas Instruments Incorporated
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This document contains information which may be changed at any time without notice
TI [ TEXAS INSTRUMENTS ]
