DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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BUFFER
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
TYPE [13]
STATE [10]
F9
VIN[0]A_D[20]
VIN[0]A_D[20]
PINCNTL160 /
0x4814 0A7C
0x000C 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x01
I
PIN
PIN
0
L
L
L
L
L
DVDD_C
CAM_D[12]
0x02
0x08
0x20
0x80
0x01
0x02
0x08
0x20
0x80
0x01
0x02
0x08
0x20
0x80
0x01
0x02
0x08
0x20
0x80
0x01
0x10
0x40
0x80
0x01
0x02
0x80
0x01
0x80
0x01
0x20
0x80
0x01
0x20
0x80
0x01
0x20
0x80
I
EMAC[1]_RMCRSDV
SPI[3]_SCS[0]
GP0[14]
I
I/O
I/O
I
1
PIN
PIN
PIN
PIN
1
C7
A6
A5
VIN[0]A_D[21]
VIN[0]A_D[22]
VIN[0]A_D[23]
VIN[0]A_D[21]
CAM_D[13]
PINCNTL161 /
0x4814 0A80
L
L
L
DVDD_C
DVDD_C
DVDD_C
I
EMAC[1]_RMTXD[0]
SPI[3]_SCLK
GP0[15]
O
I/O
I/O
I
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
0
VIN[0]A_D[22]
CAM_D[14]
PINCNTL162 /
0x4814 0A84
I
EMAC[1]_RMTXD[1]
SPI[3]_D[1]
O
I/O
I/O
I
GP0[16]
VIN[0]A_D[23]
CAM_D[15]
PINCNTL163 /
0x4814 0A88
I
EMAC[1]_RMTXEN
SPI[3]_D[0]
O
I/O
I/O
I
GP0[17]
C12
B5
VIN[0]A_DE
VIN[0]A_DE
VIN[0]A_DE
VIN[0]B_HSYNC
I2C[2]_SDA
PINCNTL135 /
0x4814 0A18
0x000E 0000
0x0006 0000
H
H
H
H
DVDD
I
0
I/O
I/O
I
1
GP2[0]
PIN
0
VIN[0]A_DE
CAM_D[7]
PINCNTL164 /
0x4814 0A8C
DVDD_C
I
PIN
PIN
PIN
PIN
PIN
0
GP0[18]
I/O
I
E16
H17
VIN[0]A_D[10]_BD[2]
VIN[0]A_D[11]_BD[3]
VIN[0]A_D[10]_BD[2]
GP2[15]
PINCNTL150 /
0x4814 0A54
0x000C 0000
0x000C 0000
L
L
L
L
DVDD
DVDD
I/O
I
VIN[0]A_D[11]_BD[3]
CAM_WE
PINCNTL151 /
0x4814 0A58
I
GP2[16]
I/O
I
PIN
PIN
PIN
PIN
PIN
0
J16
VIN[0]A_D[12]_BD[4]
VIN[0]A_D[13]_BD[5]
VIN[0]A_D[12]_BD[4]
CLKOUT1
PINCNTL152 /
0x4814 0A5C
0x0004 0000
0x000C 0000
L
L
L
L
DVDD
DVDD
I/O
I/O
I
GP2[17]
H16
VIN[0]A_D[13]_BD[5]
CAM_RESET
GP2[18]
PINCNTL153 /
0x4814 0A60
I/O
I/O
PIN
54
Device Pins
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