DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BUFFER
TYPE [13]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
STATE [10]
F13
VIN[0]A_D[14]_BD[6]
VIN[0]A_D[14]_BD[6]
PINCNTL154 /
0x4814 0A64
0x000C 0000
0x000C 0000
0x01
I
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
0
L
L
DVDD
DVDD
CAM_STROBE
GP2[19]
0x20
0x80
0x01
0x20
0x80
0x01
0x80
0x01
0x80
0x01
0x10
0x40
0x80
0x01
0x02
0x80
0x01
0x80
0x01
0x80
0x01
0x20
0x80
0x01
0x02
0x80
0x01
0x02
0x80
0x01
0x02
0x10
0x40
0x80
0x01
0x02
0x80
O
I/O
I
H13
VIN[0]A_D[15]_BD[7]
VIN[0]A_D[15]_BD[7]
CAM_SHUTTER
GP2[20]
PINCNTL155 /
0x4814 0A68
L
L
O
I/O
I
B16
C16
J13
VIN[0]A_D[8]_BD[0]
VIN[0]A_D[9]_BD[1]
VIN[0]A_FLD
VIN[0]A_D[8]_BD[0]
GP2[13]
PINCNTL148 /
0x4814 0A4C
0x000C 0000
0x000C 0000
0x000E 0000
L
L
H
L
L
H
DVDD
DVDD
DVDD
I/O
I
VIN[0]A_D[9]_BD[1]
GP2[14]
PINCNTL149 /
0x4814 0A50
I/O
I
VIN[0]A_FLD
VIN[0]B_VSYNC
I2C[2]_SCL
GP2[1]
PINCNTL136 /
0x4814 0A1C
I
0
I/O
I/O
I
1
PIN
0
B4
VIN[0]A_FLD
VIN[0]A_FLD
CAM_D[5]
PINCNTL166 /
0x4814 0A94
0x0006 0000
H
H
DVDD_C
I
PIN
PIN
0
GP0[20]
I/O
I
D13
C13
H12
VIN[0]A_HSYNC
VIN[0]A_VSYNC
VIN[0]B_CLK
VIN[0]A_HSYNC
GP2[3]
PINCNTL138 /
0x4814 0A24
0x000E 0000
0x000E 0000
0x0004 0000
H
H
L
H
H
L
DVDD
DVDD
DVDD
I/O
I
PIN
0
VIN[0]A_VSYNC
GP2[4]
PINCNTL139 /
0x4814 0A28
I/O
I
PIN
0
VIN[0]B_CLK
CLKOUT0
PINCNTL134 /
0x4814 0A14
O
I/O
I
PIN
PIN
0
GP1[9]
C5
VIN[0]B_DE
VIN[0]B_DE
CAM_D[6]
PINCNTL165 /
0x4814 0A90
0x0006 0000
0x0006 0000
0x000C 0000
H
H
L
H
H
L
DVDD_C
DVDD_C
DVDD
I
PIN
PIN
0
GP0[19]
I/O
I
A3
VIN[0]B_FLD
VOUT[0]_AVID
VIN[0]B_FLD
CAM_D[4]
PINCNTL167 /
0x4814 0A98
I
PIN
PIN
PIN
PIN
1
GP0[21]
I/O
O
O
I/O
I/O
I/O
O
I/O
I/O
C20
VOUT[0]_AVID
VOUT[0]_FLD
SPI[3]_SCLK
TIM7_IO
PINCNTL179 /
0x4814 0AC8
PIN
PIN
PIN
1
GP2[21]
F24
VOUT[0]_B_CB_C[2]
VOUT[0]_B_CB_C[2]
EMU2
PINCNTL180 /
0x4814 0ACC
0x000C 0000
L
L
DVDD
GP2[22]
PIN
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