DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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BUFFER
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
TYPE [13]
STATE [10]
AA29
SD0_CMD
SD0_CMD
SD1_CMD
GP0[2]
PINCNTL9 /
0x4814 0820
0x000E 0000
0x000E 0000
0x000E 0000
0x01
O
1
H
H
H
H
DVDD_SD
0x02
0x80
0x01
0x02
0x80
0x01
0x02
0x80
0x02
0x80
0x02
0x80
0x01
0x02
0x80
0x01
0x02
0x80
0x01
O
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
AA28
Y30
SD0_DAT[0]
SD0_DAT[3]
SD0_DAT[0]
SD1_DAT[4]
GP0[3]
PINCNTL10 /
0x4814 0824
H
H
DVDD_SD
DVDD_SD
SD0_DAT[3]
SD1_DAT[7]
GP0[6]
PINCNTL13 /
0x4814 0830
AB31
AC30
AA26
SD0_DAT[6]
SD0_DAT[6]
GP0[12]
PINCNTL41 /
0x4814 08A0
0x000E 0000
0x000E 0000
0x000E 0000
H
H
H
H
H
H
DVDD_SD
DVDD_SD
DVDD_SD
SD0_DAT[7]
SD0_DAT[7]
GP0[13]
PINCNTL42 /
0x4814 08A4
SD0_DAT[1]_SDIRQ
SD0_DAT[1]_SDIRQ
SD1_DAT[5]
GP0[4]
PINCNTL11 /
0x4814 0828
Y31
SD0_DAT[2]_SDRW
SD0_DAT[2]_SDRW
SD1_DAT[6]
GP0[5]
PINCNTL12 /
0x4814 082C
0x000E 0000
H
H
DVDD_SD
W30
Y29
SD1_CLK
SD1_CMD
SD1_CLK
PINCNTL1 /
0x4814 0800
0x0006 0000
0x000E 0000
H
H
H
H
DVDD_SD
DVDD_SD
SD1_CMD
GP0[0]
PINCNTL2 /
0x4814 0804
0x01
0x80
0x01
O
1
I/O
I/O
PIN
PIN
W31
Y27
SD1_DAT[0]
SD1_DAT[0]
PINCNTL3 /
0x4814 0808
0x000E 0000
0x000E 0000
0x000E 0000
0x000E 0000
0x0006 0000
H
H
H
H
H
H
H
H
H
H
DVDD_SD
DVDD_SD
DVDD_SD
DVDD_SD
DVDD_RGMII
SD1_DAT[3]
SD1_DAT[3]
PINCNTL6 /
0x4814 0814
0x01
0x01
0x01
I/O
I/O
I/O
PIN
PIN
PIN
AA30
U29
AC4
SD1_DAT[1]_SDIRQ
SD1_DAT[2]_SDRW
SD2_DAT[0]
SD1_DAT[1]_SDIRQ
SD1_DAT[2]_SDRW
PINCNTL4 /
0x4814 080C
PINCNTL5 /
0x4814 0810
SD2_DAT[0]
GPMC_A[4]
GP1[14]
PINCNTL120 /
0x4814 09DC
0x01
0x02
0x80
0x01
0x02
0x80
O
PIN
PIN
PIN
PIN
PIN
PIN
O
I/O
I/O
O
AD1
SD2_DAT[3]
SD2_DAT[3]
GPMC_A[1]
GP2[5]
PINCNTL117 /
0x4814 09D0
0x0006 0000
H
H
DVDD_RGMII
I/O
48
Device Pins
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