DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL
RESET
REL.
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
BALL
RESET
STATE [9]
MODE
[6]
BUFFER
TYPE [13]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [7] DSIS [8]
POWER [11]
HYS [12]
STATE [10]
AD2
SD2_DAT[4]
SD2_DAT[4]
PINCNTL116 /
0x4814 09CC
0x0006 0000
0x01
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
H
H
DVDD_RGMII
GPMC_A[27]
GPMC_A[23]
GPMC_CS[7]
EDMA_EVT0
TIM7_IO
0x02
0x04
0x08
0x20
0x40
0x80
0x01
0x02
0x04
0x40
0x80
0x01
0x02
0x04
0x20
0x80
0x01
0x02
0x04
0x20
0x80
0x01
0x02
0x80
0x01
0x02
0x80
0x01
0x80
0x01
O
O
I
I/O
I/O
I/O
O
GP1[22]
AE1
AE2
AE3
SD2_DAT[5]
SD2_DAT[6]
SD2_DAT[7]
SD2_DAT[5]
GPMC_A[26]
GPMC_A[22]
TIM6_IO
PINCNTL115 /
0x4814 09C8
0x0006 0000
0x0006 0000
0x0006 0000
H
H
H
H
H
H
DVDD_RGMII
DVDD_RGMII
DVDD_RGMII
O
I/O
I/O
I/O
O
GP1[21]
SD2_DAT[6]
GPMC_A[25]
GPMC_A[21]
UART2_TXD
GP1[20]
PINCNTL114 /
0x4814 09C4
O
O
I/O
I/O
O
SD2_DAT[7]
GPMC_A[24]
GPMC_A[20]
UART2_RXD
GP1[19]
PINCNTL113 /
0x4814 09C0
O
I
I/O
I/O
O
PIN
PIN
PIN
PIN
PIN
PIN
PIN
1
AC5
AC8
AC6
SD2_DAT[1]_SDIRQ
SD2_DAT[2]_SDRW
SD2_SCLK
SD2_DAT[1]_SDIRQ
GPMC_A[3]
GP1[13]
PINCNTL119 /
0x4814 09D8
0x0006 0000
0x0006 0000
0x0006 0000
H
H
H
H
H
H
DVDD_RGMII
DVDD_RGMII
DVDD_RGMII
I/O
I/O
O
SD2_DAT[2]_SDRW
GPMC_A[2]
GP2[6]
PINCNTL118 /
0x4814 09D4
I/O
I/O
I/O
I
SD2_SCLK
GP1[15]
PINCNTL121 /
0x4814 09E0
PIN
NA
H31
H30
J28
J27
N24
SERDES_CLKN
SERDES_CLKP
SPI[0]_D[0]
SERDES_CLKN
NA /
NA
NA
NA
NA
H
NA
NA
H
VDDA_SATA0_1P8
VDDA_SATA0_1P8
DVDD
SERDES_CLKP
SPI[0]_D[0]
NA /
NA
NA
0x01
0x01
0x01
0x01
I
NA
PINCNTL84 /
0x4814 094C
0x0006 0000
0x0006 0000
0x0006 0000
I/O
I/O
I/O
PIN
PIN
PIN
SPI[0]_D[1]
SPI[0]_D[1]
PINCNTL83 /
0x4814 0948
H
H
DVDD
SPI[0]_SCLK
SPI[0]_SCLK
PINCNTL82 /
0x4814 0944
H
H
DVDD
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