DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 3-10. AAR Ball Map [Section Bottom_Right - Top View]
AE
AF
AG
AH
AJ
AK
AL
15
14
13
12
11
10
9
DVDD_DDR[0]
DDR[0]_D[17]
DVDD_DDR[0]
DDR[0]_D[16]
DDR[0]_DQM[2]
DDR[0]_DQS[1]
DDR[0]_D[15]
DDR[0]_D[12]
DDR[0]_DQM[1]
DDR[0]_DQS[0]
DDR[0]_D[2]
DDR[0]_D[1]
DDR[0]_DQS[1]
DDR[0]_D[14]
VSS
VSS
DDR[0]_D[9]
VSS
VSS
DDR[0]_D[8]
DDR[0]_D[3]
DDR[0]_D[7]
DDR[0]_D[6]
DDR[0]_D[4]
DDR[0]_DQS[0]
VSS
VSS
VSS
VSS
VSS
DDR[0]_D[0]
8
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]
DDR[0]_DQM[0]
7
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL
VSS
VSS
VSS
6
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC
GPMC_CS[4]
5
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]
4
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]
EMAC[0]_MTCLK/
EMAC[0]_RGRXC
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]
3
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]
SD2_DAT[7]
SD2_DAT[6]
SD2_DAT[5]
MDIO
MDCLK
2
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]
GPMC_CS[3]
1
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL
EMAC[0]_MRCLK/
EMAC[0]_RGTXC
EMAC_RMREFCLK
VSS
Ball Map Position
1
6
2
7
3
8
4
9
5
10
32
Device Pins
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