DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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DDR2
DQ0
DDR[0]_D[0]
DDR[0]_D[7]
DQ7
LDM
LDQS
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
DDR[0]_D[8]
LDQS
DQ8
DDR[0]_D[15]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DQ15
UDM
UDQS
UDQS
DDR[0]_ODT[0]
DDR[0]_D[16]
T0
NC
ODT
Vio 1.8(A)
DDR[0]_D[23]
NC
NC
DDR[0]_DQM[2]
1 KΩ
1 KΩ
DDR[0]_DQS[2]
DDR[0]_DQS[2]
NC
DDR[0]_D[24]
Vio 1.8(A)
DDR[0]_D[31]
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
NC
NC
1 KΩ
1 KΩ
DDR[0]_BA[0]
T0
BA0
DDR[0]_BA[2]
DDR[0]_A[0]
T0
T0
BA2
A0
DDR[0]_A[15]
DDR[0]_CS[0]
T0
T0
A15
CS
DDR[0]_CAS
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_CLK
CAS
RAS
T0
T0
T0
T0
T0
T0
Vio 1.8(A)
WE
CKE
CK
CK
1 K Ω 1%
0.1 µF
0.1 µF
DDR[0]_CLK
VREFSSTL_DDR[0]
VREF VREF
VREF
0.1 µF(B)
0.1 µF(B)
1 K Ω 1%
DDR[0]_RST
DDR[0]_VTP
NC
50 Ω ( 2%)
T0
Termination is required. See terminator comments.
A. Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-49. 16-Bit DDR2 High-Level Schematic
220
Peripheral Information and Timings
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