DM385, DM388
www.ti.com
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
DDR2
DQ0
DDR[0]_D[0]
DDR[0]_D[7]
DQ7
LDM
LDQS
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
DDR[0]_D[8]
LDQS
DQ8
DDR[0]_D[15]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DQ15
UDM
UDQS
UDQS
ODT
DDR[0]_DQS[1]
DDR[0]_ODT[0]
T0
DDR2
ODT
DDR[0]_D[16]
DQ0
DDR[0]_D[23]
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DQ7
LDM
LDQS
DDR[0]_DQS[2]
DDR[0]_D[24]
LDQS
DQ8
DDR[0]_D[31]
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DQ15
UDM
UDQS
UDQS
DDR[0]_BA[0]
T0
BA0
BA0
DDR[0]_BA[2]
DDR[0]_A[0]
T0
T0
BA2
A0
BA2
A0
DDR[0]_A[15]
DDR[0]_CS[0]
T0
T0
A15
CS
A15
CS
Vio 1.8(A)
DDR[0]_CAS
DDR[0]_RAS
CAS
RAS
T0
T0
T0
T0
T0
T0
CAS
RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_CLK
WE
WE
CKE
CKE
0.1 µF
0.1 µF
1 K Ω 1%
CK
CK
CK
CK
DDR[0]_CLK
VREF VREF
VREF VREF
VREFSSTL_DDR[0]
VREF
0.1 µF(B)
0.1 µF(B)
0.1 µF(B)
1 K Ω 1%
DDR[0]_RST
DDR[0]_VTP
NC
50 Ω ( 2%)
T0
Termination is required. See terminator comments.
A. Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-48. 32-Bit DDR2 High-Level Schematic
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
219
Submit Documentation Feedback
Product Folder Links: DM385 DM388
TI [ TEXAS INSTRUMENTS ]
