DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Table 2-5. L4 Slow Peripheral Memory Map (continued)
Cortex-A8 and L3 Masters
SIZE
DEVICE NAME
START ADDRESS
END ADDRESS
(HEX)
(HEX)
0x481E_9000
0x4820_0000
0x4820_1000
0x4824_0000
0x4824_1000
0x4828_0000
0x4828_1000
0x4830_0000
0x481F_FFFF
0x4820_0FFF
0x4823_FFFF
0x4824_0FFF
0x4827_FFFF
0x4828_0FFF
0x482F_FFFF
0x48FF_FFFF
52KB
4KB
Reserved
Interrupt controller(1)
Reserved(1)
MPUSS config register(1)
Reserved(1)
SSM(1)
Reserved(1)
252KB
4KB
252KB
4KB
508KB
13MB
Reserved
(1) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only
for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.
2.10.3 DDR DMM TILER Extended Addressing Map
The Tiler includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access
the frame buffer in rotated and mirrored views. shows the details of the Tiler Extended Address Mapping.
This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However,
other masters can access any one single view through the 512-MB Tiler region in the base 4GByte
address memory map.
Table 2-6. DDR DMM TILER Extended Address Mapping
START ADDRESS
(HEX)
END ADDRESS
(HEX)
BLOCK NAME
SIZE
DESCRIPTION
Tiler View 0
Tiler View 1
0x1 0000_0000
0x1 2000_0000
0x1 1FFF_FFFF
0x1 3FFF_FFFF
512MB
512MB
Natural 0° View
0° with Vertical Mirror
View
Tiler View 2
0x1 4000_0000
0x1 5FFF_FFFF
512MB
0° with Horizontal Mirror
View
Tiler View 3
Tiler View 4
0x1 6000_0000
0x1 8000_0000
0x1 7FFF_FFFF
0x1 9FFF_FFFF
512MB
512MB
180° View
90° with Vertical Mirror
View
Tiler View 5
Tiler View 6
Tiler View 7
0x1 A000_0000
0x1 C000_0000
0x1 E000_0000
0x1 BFFF_FFFF
0x1 DFFF_FFFF
0x1 FFFF_FFFF
512MB
512MB
512MB
270° View
90° View
90° with Horizontal Mirror
View
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