DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
2.10.2.2 L4 Slow Peripheral Memory Map
Table 2-5. L4 Slow Peripheral Memory Map
Cortex-A8 and L3 Masters
SIZE
DEVICE NAME
START ADDRESS
END ADDRESS
(HEX)
(HEX)
0x4800_0000
0x4800_0800
0x4800_1000
0x4800_1400
0x4800_1800
0x4800_2000
0x4800_8000
0x4801_0000
0x4801_1000
0x4801_2000
0x4802_0000
0x4802_1000
0x4802_2000
0x4802_3000
0x4802_4000
0x4802_5000
0x4802_6000
0x4802_8000
0x4802_9000
0x4802_A000
0x4802_B000
0x4802_C000
0x4802_E000
0x4802_F000
0x4803_0000
0x4803_1000
0x4803_2000
0x4803_3000
0x4803_4000
0x4803_8000
0x4803_A000
0x4803_B000
0x4803_C000
0x4803_E000
0x4803_F000
0x4804_0000
0x4804_1000
0x4804_2000
0x4804_3000
0x4804_4000
0x4804_5000
0x4804_6000
0x4804_7000
0x4800_07FF
0x4800_0FFF
0x4800_13FF
0x4800_17FF
0x4800_1FFF
0x4800_7FFF
0x4800_8FFF
0x4801_0FFF
0x4801_1FFF
0x4801_FFFF
0x4802_0FFF
0x4802_1FFF
0x4802_2FFF
0x4802_3FFF
0x4802_4FFF
0x4802_5FFF
0x4802_7FFF
0x4802_8FFF
0x4802_9FFF
0x4802_AFFF
0x4802_BFFF
0x4802_DFFF
0x4802_EFFF
0x4802_FFFF
0x4803_0FFF
0x4803_1FFF
0x4803_2FFF
0x4803_3FFF
0x4803_7FFF
0x4803_9FFF
0x4803_AFFF
0x4803_BFFF
0x4803_DFFF
0x4803_EFFF
0x4803_FFFF
0x4804_0FFF
0x4804_1FFF
0x4804_2FFF
0x4804_3FFF
0x4804_4FFF
0x4804_5FFF
0x4804_6FFF
0x4804_7FFF
2KB
2KB
1KB
1KB
2KB
24KB
32KB
4KB
4KB
56KB
4KB
4KB
4KB
4KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
4KB
4KB
16KB
8KB
4KB
4KB
8KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
L4 Slow Configuration – Address/Protection (AP)
L4 Slow Configuration – Link Agent (LA)
L4 Slow Configuration – Initiator Port (IP0)
L4 Slow Configuration – Initiator Port (IP1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UART0 Peripheral Registers
UART0 Interconnect Registers
UART1 Peripheral Registers
UART1 Interconnect Registers
UART2 Peripheral Registers
UART2 Interconnect Registers
Reserved
I2C0 Peripheral Registers
I2C0 Interconnect Registers
I2C1 Peripheral Registers
I2C1 Interconnect Registers
Reserved
TIMER1 Peripheral Registers
TIMER1 Interconnect Registers
SPI0 Peripheral Registers
SPI0 Interconnect Registers
GPIO0 Peripheral Registers
GPIO0 Interconnect Registers
Reserved
McASP0 CFG Peripheral Registers
McASP0 CFG Interconnect Registers
Reserved
McASP1 CFG Peripheral Registers
McASP1 CFG Interconnect Registers
Reserved
TIMER2 Peripheral Registers
TIMER2 Interconnect Registers
TIMER3 Peripheral Registers
TIMER3 Interconnect Registers
TIMER4 Peripheral Registers
TIMER4 Interconnect Registers
TIMER5 Peripheral Registers
TIMER5 Interconnect Registers
18
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