DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
2.10.2 L4 Memory Map
The L4 Fast Peripheral Domain and L4 Slow Peripheral Domain regions of the memory maps above are
broken out into Table 2-4 and Table 2-5.
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see ,
System Interconnect.
2.10.2.1 L4 Fast Peripheral Memory Map
Table 2-4. L4 Fast Peripheral Memory Map
Cortex-A8 and L3 Masters
SIZE
DEVICE NAME
START ADDRESS
(HEX)
END ADDRESS
(HEX)
0x4A00_0000
0x4A00_0800
0x4A00_1000
0x4A00_1400
0x4A00_1800
0x4A00_2000
0x4A08_0000
0x4A0A_0000
0x4A0A_E000
0x4A10_0000
0x4A10_8000
0x4A14_0000
0x4A15_0000
0x4A15_1000
0x4A18_0000
0x4A1A_2000
0x4A1A_4000
0x4A1A_5000
0x4A1A_6000
0x4A1A_7000
0x4A1A_8000
0x4A1A_A000
0x4A1A_B000
0x4A1A_C000
0x4A1A_D000
0x4A1A_E000
0x4A1B_0000
0x4A1B_1000
0x4A1B_2000
0x4A1B_3000
0x4A1B_6000
0x4A1B_4000
0x4A00_07FF
0x4A00_0FFF
0x4A00_13FF
0x4A00_17FF
0x4A00_1FFF
0x4A07_FFFF
0x4A09_FFFF
0x4A0A_0FFF
0x4A0F_FFFF
0x4A10_7FFF
0x4A10_8FFF
0x4A14_FFFF
0x4A15_0FFF
0x4A17_FFFF
0x4A1A_1FFF
0x4A1A_3FFF
0x4A1A_4FFF
0x4A1A_5FFF
0x4A1A_6FFF
0x4A1A_7FFF
0x4A1A_9FFF
0x4A1A_AFFF
0x4A1A_BFFF
0x4A1A_CFFF
0x4A1A_DFFF
0x4A1A_FFFF
0x4A1B_0FFF
0x4A1B_1FFF
0x4A1B_2FFF
0x4A1B_5FFF
0x4A1B_6FFF
0x4AFF_FFFF
2KB
2KB
L4 Fast Configuration - Address/Protection (AP)
L4 Fast Configuration - Link Agent (LA)
1KB
L4 Fast Configuration - Initiator Port (IP0)
1KB
L4 Fast Configuration - Initiator Port (IP1)
2KB
Reserved
504KB
128KB
4KB
Reserved
Reserved
Reserved
380KB
32KB
4KB
Reserved
EMAC SW Peripheral Registers
EMAC SW Interconnect Registers
Reserved
64KB
4KB
Reserved
188KB
136KB
8KB
Reserved
Reserved
Reserved
4KB
Reserved
4KB
Reserved
4KB
Reserved
4KB
Reserved
8KB
Reserved
4KB
Reserved
4KB
Reserved
4KB
Reserved
4KB
Reserved
8KB
Reserved
4KB
Reserved
4KB
Reserved
4KB
Reserved
12KB
4KB
Reserved
Reserved
14632KB
Reserved
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