DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 8-37. Static and Dynamic SD-DAC Specifications
VDAC STATIC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
4653
9900
2673
TYP
4700
10000
2700
MAX
4747
10100
2727
UNIT
Ω
Reference Current Setting Resistor Normal Mode
(RSET
)
TVOUT Bypass Mode
Ω
Output resistor between TV_OUT0 Normal Mode
Ω
and TV_VFB0 pins (ROUT
)
TVOUT Bypass Mode
Normal Mode
N/A
Load Resistor (RLOAD
)
75-Ω Inside the Display
TVOUT Bypass Mode
Normal Mode
1485
220
1500
1515
Ω
AC-Coupling Capacitor (Optional)
[CAC
uF
]
TVOUT Bypass Mode
Normal Mode
See External Amplifier Specification
Total Capacitance from TV_OUT0
to VSSA_VDAC_1P8
300
pF
TVOUT Bypass Mode
N/A
Resolution
10
Bits
LSB
LSB
LSB
LSB
V
Integral Non-Linearity (INL), Best
Fit
Normal Mode
-4
-1
4
TVOUT Bypass Mode
Normal Mode
1
Differential Non-Linearity (DNL)
-2.5
-1
2.5
1
TVOUT Bypass Mode
Normal Mode (RLOAD = 75 Ω)
Full-Scale Output Voltage
1.3
TVOUT Bypass Mode (RLOAD
1.5 kΩ)
=
0.7
V
Full-Scale Output Current
Normal Mode
N/A
-10
TVOUT Bypass Mode
470
uA
%FS
Ω
Gain Error
Normal Mode (Composite) and
TVOUT Bypass Mode
10
Output Impedance
Looking into TV_OUT0 nodes
75
VDAC DYNAMIC SPECIFICATIONS
TEST CONDITIONS MIN
PARAMETER
TYP
54
6
MAX
UNIT
MHz
MHz
Output Update Rate (FCLK
)
60
Signal Bandwidth
3 dB
Spurious-Free Dynamic Range
(SFDR) within bandwidth
FCLK = 54 MHz, FOUT = 1 MHz
50
54
6
dBc
dB
Signal-to-Noise Ration (SNR)
FCLK = 54 MHz, FOUT = 1 MHz
Normal Mode, 100 mVpp @ 6
MHz on VDDA_VDAC_1P8
Power Supply Rejection (PSR)
dB
TVOUT Bypass Mode, 100
mVpp @ 6 MHz on
20
VDDA_VDAC_1P8
206
Peripheral Information and Timings
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