DM385, DM388
www.ti.com
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
GPMC_A[27:16]
GPMC_BE1
5
7
Address (MSB)
8
8
20
Valid
7
20
Valid
GPMC_BE0_CLE
9
9
10
12
21
GPMC_ADV_ALE
GPMC_OE
11
14
13
13
13
13
5
6
GPMC_D[15:0]
(Multplexed Mode)
Address (LSB)
D0
22
D1
D2
D3
23
GPMC_WAIT[x]
Figure 8-25. GPMC Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read (GPMCFCLKDIVIDER = 0)
2
2
1
GPMC_CLK
GPMC_CS[x]
3
4
19
5
7
6
GPMC_A[27:16]
GPMC_BE1
Address (MSB)
18
18
18
18
18
18
7
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
GPMC_WE
15
15
16
6,16
5
16
16
GPMC_D[15:0]
(Multiplexed Mode)
Address (LSB)
D0
D1
22
D2
D3
23
GPMC_WAIT[x]
Figure 8-26. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
8.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing (Non-Multiplexed and Multiplexed
Modes)
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
189
Submit Documentation Feedback
Product Folder Links: DM385 DM388
TI [ TEXAS INSTRUMENTS ]
