DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
2
2
1
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:0]
GPMC_BE1
Address
7
7
18
18
18
18
18
18
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
GPMC_WE
15
15
16
16
16
16
GPMC_D[15:0]
(Non-Multiplexed Mode)
D0
23
D1
22
D2
D3
GPMC_WAIT[x]
Figure 8-23. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
7
GPMC_A[27:16]
Address
20
8
8
GPMC_BE1
7
20
GPMC_BE0_CLE
9
9
21
10
12
GPMC_ADV_ALE
GPMC_OE
11
5
6
13
14
GPMC_D[15:0]
(Multiplexed Mode)
Address (LSB)
23
D0
22
GPMC_WAIT[x]
Figure 8-24. GPMC Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)
188
Peripheral Information and Timings
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