DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
7
GPMC_A[27:0]
Address
8
8
20
GPMC_BE1
7
20
GPMC_BE0_CLE
9
9
21
10
12
GPMC_ADV_ALE
GPMC_OE
11
14
13
GPMC_D[15:0]
GPMC_WAIT[x]
D0
22
23
Figure 8-21. GPMC Non-Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:0]
GPMC_BE1
Address
20
8
8
7
7
Valid
20
Valid
GPMC_BE0_CLE
9
9
10
12
21
GPMC_ADV_ALE
GPMC_OE
11
14
13
13
13
13
GPMC_D[15:0]
(Non-Multplexed Mode)
D0
22
D1
D2
D3
23
GPMC_WAIT[x]
Figure 8-22. GPMC Non-Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read
(GPMCFCLKDIVIDER = 0)
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Peripheral Information and Timings
187
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