DM385, DM388
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GPMC_FCLK
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
GPMC_CLK
2
GPMC_CS[x]
10
11
GPMC_A[10:1]
Valid Address
1
GPMC_BE1
GPMC_BE0_CLE
GPMC_ADV_ALE
11
1
4
13
28
26
GPMC_WE
30
GPMC_D[15:0]
Data OUT
GPMC_WAIT[x]
Figure 8-30. GPMC/Non-Multiplexed NOR Flash - Asynchronous Write - Single Word Timing
GPMC_FCLK
GPMC_CLK
2
6
GPMC_CS[x]
10
11
Address (MSB)
1
GPMC_A[26:17]
GPMC_BE1
11
1
GPMC_BE0_CLE
13
4
GPMC_ADV_ALE
GPMC_OE
5
14
30
38
GPMC_A[16:1]
GPMC_D[15:0]
Address (LSB)
Data IN
Data IN
GPMC_WAIT[x]
Figure 8-31. GPMC/Multiplexed NOR Flash - Asynchronous Read - Single Word Timing
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Peripheral Information and Timings
193
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