DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
8.8 General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
The GPMC is a device memory controller used to provide a glueless interface to external memory devices
such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND
Flash), SRAM, and Pseudo-SRAM. It includes flexible asynchronous protocol control for interface to
SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).
Other supported features include:
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8-/16-bit wide multiplexed address/data bus
512 MBytes maximum addressing capability divided among up to eight chip selects
Non-multiplexed address/data mode
Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
The device also contains an Error Locator Module (ELM) which is used to extract error addresses from
syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the
read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus
optionally spare area information. The ELM has the following features:
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4-bit, 8-bit and 16-bit per 512byte block error location based on BCH algorithms
Eight simultaneous processing contexts
Page-based and continuous modes
Interrupt generation on error location process completion
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When the full page has been processed in page mode
For each syndrome polynomial in continuous mode
8.8.1 GPMC and ELM Peripherals Register Descriptions
The GPMC and ELM peripheral registers are described in the device-specific Technical Reference
Manual. Each register is documented as an offset from a base address for the peripheral. The base
addresses for all of the peripherals are in the device memory map (see Section 2.10).
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
183
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